1. Field of the Invention
The present invention relates to a circuit layout device, circuit layout method and a program for executing this circuit layout method, and more particularly to a circuit layout device, circuit layout method and a program for executing this circuit layout method of an integrated circuit having scan chains.
2. Description of the Related Art
Recently a scan type test circuit is often mounted to simplify testing of a semiconductor device as semiconductor devices become faster and a density of semiconductor circuit is enlarged. In the case of a conventional circuit, when circuit layout is decided, layout is considered so that wiring in the user circuit block becomes short, without considering wiring of the scan chain. The wiring of the scan chains is generally decreased in rechaining, which is for reconnecting the scan chains after circuit layout is decided.
An example of considering the scan chains in a circuit layout is disclosed in Japanese Unexamined Patent Application Publication No. 3-135067. The technology disclosed in Japanese Unexamined Patent Application Publication No. 3-135067 distributes scan gates considering the routability of the user circuits, and no consideration is made here to minimize the wires of the scan chains.
Recently, however, to decrease the test time, the number of scan chains to be set for one semiconductor device is increasing. In some cases several hundred or even several thousand of scan chains may be prepared for one semiconductor device. In such a semiconductor device, the man power to rechain the scan chains after circuit layout is decided would be enormous.
Therefore a circuit layout method that can decrease the wires of the scan chains has been desired. Minimizing the wire length of the scan chains is preferable as the number of scan chains increases.